Low skew minimized clock splitter

ABSTRACT

A clock splitter device for forming a clock/inverted clock signal pair. The input clock signal is sent through an initial buffer stage and applied to two parts of a second stage. The second stage includes a single stage buffer and constricted inverter to provide two inverted outputs. The transistor arrangement of these two parts provides an equal delay to the two signal paths. The outputs of these two parts are sent to identical output buffers. Because the two paths have identical transistor delays, and since the metal paths on the board are arranged to have identical delays, the two paths can very low skew therebetween.

FIELD

[0001] The present invention is directed to a clock generator forproducing two clock signals 180° out of phase. More particularly, thepresent invention is directed to a clock splitter which producesmultiple clock signals at different phases having low skew between themwhere the generators are made of PMOS and NMOS transistors.

BACKGROUND

[0002] Many high speed signaling components in electronic devicesutilize a fast clock frequency. In such devices, it is often necessaryto have clock signals having different phases but the same frequency.Often, the different clock signals are generated from the same originalclock signal but with one inverted or otherwise phase delayed to obtainthe necessary phase difference. While such a simple approach produces asuitable set of clock signals for many purposes, it is desirable toobtain clock signals having less skew for high speed signaling devices.

[0003] Skew in this case is defined as being a measure of the differencein the rising and falling edges of the output clock signals from thatwhich is desired. In particular, if the clock signals are designed to be180° out of phase, the rising edge of one should be at the same time asthe falling edge of the other. Thus, skew is the measure of how far outof alignment the two signals are relative to each other.

[0004] One type of disadvantageous arrangement is shown in FIG. 1. Inthis arrangement of a loaded inverter chain, an input clock signal isapplied to two different paths of inverters, one of which has an oddnumber of inversions and the other an even number. Thus, one of theoutput signals will be 180° out of phase with the other due to the extrainversion. Capacitive loads 12 are added to the inverter outputs and areadjusted so that the total delay of the inverting path matches the totaldelay of the non-inverting path. While these two paths can be adjustedin this manner to have an equal delay for a given set of parameters suchas voltage, temperature and process, these path delays will vary underother parameters. This is because the load delay was adjusted to equalthe propagation delay through an inverter but the inverter delay willvary differently than the wire or load delay for different processcorners. Accordingly, while this arrangement can be suitable for somepurposes, it does not produce a stable low skew clock signalarrangement.

[0005] Another arrangement is shown in FIG. 2A and is known as anexclusive NOR pair. In this arrangement the clock signal forms one inputto each of two gates. The other input to one gate is connected to a highvoltage (VCC) while the other input of the other gate is connected to alow voltage (VSS). Thus, since one input is always high or always low,outputs are obtained in opposite directions from the two gates. Analternative arrangement has these gates being exclusive OR gates.

[0006]FIG. 2B shows a exclusive NOR arrangement for one of the gates inFIG. 2A. In this arrangement, A is the equivalent of the “a” input ofFIG. 2A, which is connected either to the high or low voltage source.The B input is the same as the “b” input which is connected to the inputclock signal. The CO output is the same as the output “o” from the logicgates. It is clear that the actual circuitry needed for the logic gateis reasonably complex and a number of transistors must be used in orderto make such a gate. More importantly, because of the complexity of thedevice, it is difficult to balance the output to a high degree so thatthe skew between the two clock signals is minimized. Such a logic treeshown in FIG. 2B would be unbalanced with the A and B input devicesbeing in series. A typical remedy is to add complementary series treesas shown in FIG. 2A. Delay differences due to the A-input N-channeldevice being above the B-input P-channel device would be complementarycompensated by the second series stack with the B input, N-channeldevice on top. The corresponding A and B P-channel devices are alreadyin parallel. Unfortunately, the inversion created by transistors 20 and22 is not complementary compensated and thus a delayed mismatch occursbetween the two paths. Trying to compensate for this inversion createsan even more complex situation and more sensitivity to varyingparameters.

[0007] Thus, it is clear that these disadvantageous arrangements havelimitations.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The foregoing and a better understanding of the present inventionwill become apparent from the following detailed description of exampleembodiments and the claims when read in connection with the accompanyingdrawings, all forming a part of the disclosure of this invention. Whilethe foregoing and following written and illustrated disclosure focuseson disclosing example embodiments of the invention, it should be clearlyunderstood that the same is by way of illustration and example only andthat the invention is not limited thereto. The spirit and scope of thepresent invention are limited only by the terms of the appended claims.

[0009] The following represents brief descriptions of the drawings,wherein:

[0010]FIG. 1 is an example disadvantageous arrangement useful in gaininga more thorough understanding of the present invention;

[0011]FIG. 2A is an example disadvantageous arrangement useful ingaining a more thorough understanding of the present invention;

[0012]FIG. 2B is a more detailed showing of the example disadvantageousarrangement shown in FIG. 2A.

[0013]FIG. 3 is an example advantageous embodiment of the presentinvention.

[0014]FIG. 4 is an example of a layout arrangement of the advantageousembodiment shown in FIG. 3.

[0015] FIGS. 5-7 show waveforms of various signals within theadvantageous embodiment device of FIG. 3.

DETAILED DESCRIPTION

[0016] Before beginning a detailed description of the subject invention,mention of the following is in order. When appropriate, like referencenumerals and characters may be used to designate identical,corresponding or similar components in differing figure drawings.Further, in the detailed description to follow, examplesizes/models/values/ranges may be given, although the present inventionis not limited to the same. Still further, the clock and timing signalFIGS. are not drawn to scale, and instead, exemplary and critical timevalues are mentioned when appropriate. With regard to description of anytiming signals, the terms assertion and negation may be used in anintended generic sense. More particularly, such terms are used to avoidconfusion when working with a mixture of “active-low” and “active-high”signals, and to represent the fact that the invention is not limited tothe illustrated/described signals, but could be implemented with atotal/partial reversal of any of the “active-low” and “active-high”signals by a simple change in logic. More specifically, the terms“assert” or “assertion” indicate that a signal is active independent ofwhether that level is represented by a high or low voltage, while theterms “negate” or “negation” indicate that a signal is inactive. As afinal note, well known power/ground connections to ICs and othercomponents may not be shown within the FIGS. for simplicity ofillustration and discussion, and so as not to obscure the invention.Further, arrangements may be shown in block diagram form in order toavoid obscuring the invention, and also in view of the fact thatspecifics with respect to implementation of such block diagramarrangements are highly dependent upon the platform within which thepresent invention is to be implemented, i.e., such specifics should bewell within purview of one skilled in the art. Where specific details(e.g., circuits, flowcharts) are set forth in order to describe exampleembodiments of the invention, it should be apparent to one skilled inthe art that the invention can be practiced without, or with variationof, these specific details.

[0017]FIG. 3 shows an example advantageous device according to oneembodiment of the present invention. The clock generator or clocksplitter 30 includes three stages. Stage one, 40, is an input buffer.Stage two, 50, is the splitter. Stage three is the output buffer 60.Splitter 50 includes a single stage buffer 52 and a constricted inverter54. The output buffer 60 includes two buffers 62 and 64.

[0018] An input clock signal CLKIN is received from a clock source. Itis desired to produce two output clock signals having the same frequencyas the input but being 180° out of phase and with low skew between thetwo output signals. Skew is a measure of the difference in the risingand falling edges of the output clock signals from that desired. Inparticular, it is desirable, since the clock signals are 180° out ofphase, that the rising edge of one be at the same time as the fallingedge of the other. Skew is the measure of how far out of alignment thetwo signals are.

[0019] In order to reduce the skew, it is preferable to match as closelyas possible the delay time in the two branches of the splitter. This isaccomplished by first having circuits which are balanced in a fashion sothat the time spent within corresponding parts of the circuitry are thesame on each branch and secondly that the metal paths in the layout arematched so that the time necessary for traveling between stages on thedie is also the same in both paths. Both of these concepts are involvedin the present advantageous example.

[0020] Input buffer 40 receives the CLKIN signal which is the originalsignal for the splitter. The signal is applied to PMOS device 42 and atthe same time applied to NMOS device 44. (PMOS FETs are indicated withsmall circles at the gate electrode). PMOS device 42 is also connectedat one terminal to VCC, which is the high logic voltage level for thesystem and may be 1.8 volts, for example. The third terminal of the PMOSdevice 42 is connected to the output line CLKINNN of the input bufferstage. NMOS device 44 is connected on one terminal to a voltage sourceVSS, which is the low logic level for the system and is typicallyground. The other terminal is connected to the output line CLKINNN. Inoperation, the input clock signal is applied to the gates of both PMOSdevice 42 and NMOS device 44 at the same time. Depending on whether theclock signal is at a high or low point, one of these two transistorswill be turned on and the other turned off. When this happens, theoutput line of the input buffer will be connected to either VCC or VSS,depending on which of the two transistors are conducting. However, thisbuffer acts as an inverter so the output is the inverse of the inputsignal. This buffer is essentially a standard CMOS inverter. However,the two transistors are sized relative to each other (i.e. inproportion) to give equal rise and fall edge rates.

[0021] The output signal from the input buffer is applied to both partsof splitter 50 in the second stage, namely the single stage buffer 52and the constricted inverter 54. Since the same signal is applied fromthe input buffer, as long as the delay through the two metal paths (i.e.from the output of buffer 40 to the input of 52 and from the output ofbuffer 40 to the input of 54) are equal, they will arrive at the sametime at the two ports.

[0022] The single stage buffer includes NMOS device 51 and PMOS device53. The NMOS transistor 51 is connected to VCC at one terminal and theoutput line for the buffer at the other terminal. PMOS device 53 isconnected to VSS or ground at one terminal and the same output line atthe other terminal. This buffer is similar to a regular inverter such asinput buffer 40 except that the position of the NMOS and PMOStransistors are reversed. Thus, the NMOS transistor is used as a pull upwhile the PMOS is used as a pull down. This structure passes an inputsignal without inversion but provides a similar delay to that of aregular inverter. However, the output of this single stage buffer doesnot go rail-to-rail, i.e. does not go completely from VCC to VSS. Theoutput voltage is limited by the threshold voltages of the non-idealNMOS and PMOS transistors. PMOS transistors are inefficient atdischarging a capacitive node, whereas NMOS transistors are inefficientat charging a capacitive node. This explains why the outputs of each ofthe single stage buffer and constricted inverter are not full swing.Thus, the output voltage of the signals range from (VSS+Vt_(p)) to(VCC−Vt_(n)).

[0023] At the same time, constricted inverter 54 includes PMOStransistors 55 and 57 and NMOS transistors 56 and 58. The transistors 55and 58 act as a regular inverter and are coupled in a similar fashion tothe inverter described in the input buffer 40. However, the twotransistors 56 and 57 act as threshold voltage droppers. Thus, theyfollow in the switching direction, but prevent the output from rangingall the way to VCC and VSS by dropping the threshold voltage. This isthe meaning of the word “constricted” inverter, since the output voltageis constricted by the threshold voltage. In so doing, the output voltagefollows that of the output of the single stage buffer. These transistorsalso ensure that the delay through the single stage buffer matches thedelay for the constricted inverter. However, the output of the former isa non-inverting output whereas the output of the latter is an invertedoutput.

[0024] The third stage is an output buffer 60 including two buffers 62and 64. These two buffers are substantially identical to each other.Each is an inverter and includes complementary NMOS and PMOS devices.Since these two buffers are substantially identical in construction, thedelay and the operation of the devices are substantially identical sothat the skew with respect to the two output signals CLKOUT and CLKOUTNNwill not be affected by the operation of these buffers. Accordingly, ifthe two signals from the second stage have substantially no skew withrespect to each other and identical paths are provided to the thirdstage, the third stage outputs will similarly have substantially no skewwith respect to each other. The outputs of the two buffers 62 and 64 areCLKOUT and CLKOUTNN, which are inversions of each other (or 180° out ofphase).

[0025] By utilizing properly sized transistors in relation to eachother, the delay in the two branches due to the operation in thetransistors can be matched. In addition, it is necessary to match thedelay caused by the metal paths on the die. In addition, the delay ismatched by having all of the devices oriented in the same direction andhaving devices symmetrical, that is replicated rather than mirrored. Thetransistors are replicated rather than mirrored because in thefabrication process there is often some variation along the X and Ydirections. By having the transistors replicated rather than mirrored,the variation between locations is limited. Likewise, the metal tracesforming the conductive paths are replicated as to length and total areain order to have similar delays.

[0026]FIG. 4 shows a layout of the metal paths in the advantageousexample such as shown in FIG. 3. In this layout 70, various parts of themetal tracings can be seen. The horizontal section identified as 71 isthe path through the input buffer 40 which carries the original signalCLKIN and which carries out the output signal of the first stage,CLKINNN. At its right hand end, section 71 splits into two verticalsections which correspond to the path which carries the signal to thetwo parts of the second stage. Thus, section 72 carries the signal tothe single stage buffer while second 74 carries the signal to theconstricted inverter. Section 76 carries the output of the single stagebuffer to stage three buffer 62. Likewise, section 78 carries the outputof the constricted inverter to the stage three buffer 64. Section 80then carries the output signal CLKOUT while section 82 carries outputCLKOUTNN. As can be seen, these various sections are matched in lengthin order to obtain substantially the same delay through the twodifferent paths.

[0027] By matching both the delay lines and the transistor operations,the skew is completely independent of variations in voltage temperatureand manufacturing process. That is, any changes in these parameters willresult in the same changes to both paths, thus limiting the skew. Inaddition, this device provides a simple circuit with a very small layoutand a small number of transistors. In addition, because of the smallsize in layout it can be used at several different locations within achip to provide local clock/inverted clock pairs so that it is notnecessary to try to distribute the inverted clock across the chip. Thus,the various benefits are obtained by the use of the circuitry, inaddition to the low skew inverted clock output.

[0028]FIGS. 5, 6 and 7 show waveforms of various signals within thesplitter device. In particular, FIG. 5 shows the input clock signalCLKIN which varies between 0 and 1.8 volts. FIG. 6 shows the two outputsof stage two that are inverses of each other. As can be seen in FIG. 6the outputs range between 0.4 volts on the low end and about 1.5 voltson the high end. It can be seen that these voltage values are reachedafter the transistors have switched a single time which indicates thethreshold voltage effect and indicates simulation initialization time.FIG. 7 shows the final outputs of the device, CLKOUT and CLKOUTNN. Theseinverted clock signals extend from 0 volts to 1.8 volts, approximately.As can be seen, the skew of these output signals is very low and therising and falling edges match very closely.

[0029] The clock splitter having low skew can be used anywhere where itis desired to have a clock signal/inverted clock signal pair whereaccuracy in the skew is important. Thus, this could be used in varioustypes of integrated circuits, especially in computers and other highspeed equipment. It would also especially be likely to be used in highspeed signaling components where a fast clock frequency is used. It isfurther likely to be used in logic and custom design utilizing aclock/inverted clock pair for latch or flip-flop interleaving.Accordingly, the present invention may be utilized any time whereaccuracy and high speed signaling is desired.

1. A clock splitter, comprising: an input buffer for receiving an inputclock signal; a second stage buffer: a constricted inverter, an outputof said input buffer forming an input to both said single stage bufferand said constricted inverter; a first output buffer and a second outputbuffer, said first output buffer having an input coupled to an output ofsaid single stage buffer, said second output buffer having an inputcoupled to an input of said constricted inverter.
 2. The clock splitteraccording to claim 1, wherein an output clock signal is formed at theoutput of said first output buffer and an output inverted clock signalis formed at an output of said second output buffer, said output clocksignal and said output inverted clock signal having low skew withrespect to each other.
 3. The clock splitter according to claim 1,wherein said input buffer, said first output buffer and said secondoutput buffer are CMOS inverters.
 4. The clock splitter according toclaim 1, wherein the single stage buffer includes an NMOS device coupledto the VCC and a PMOS device coupled to VSS to produce a non-invertingoutput.
 5. The clock splitter according to claim 1, wherein theconstricted inverter includes a first PMOS device coupled to VCC and afirst NMOS device coupled to VSS and a second NMOS device coupled tosaid first PMOS device and a second PMOS device coupled to said firstNMOS device.
 6. The clock splitter according to claim 1, wherein saidinput buffer, single stage buffer, constricted inverter and outputbuffer are formed of PMOS and NMOS transistors which are sized relativeto each other to give equal rise and fall edge rates.
 7. The clocksplitter according to claim 1, wherein the metal traces in the signalpaths of said clock and inverted clock signals are matched in length andarea so as to produce substantially equal delays.
 8. A method of makinga clock splitter, comprising: providing a single stage buffer and aconstricted inverter; matching transistors used in said single stagebuffer and said constricted inverter to produce equal rise and fall edgerates and to match the delay time within said single state buffer withthe delay time in said constricted inverter; matching metal tracelengths so as to produce similar delays in signal paths for outputs fromsaid single stage buffer and said constricted inverter.
 9. The methodaccording to claim 8, further comprising: providing an input buffer forreceiving an input clock signal and providing a common clock signal tosaid single stage buffer and constricted inverter.
 10. The methodaccording to claim 8, further comprising: providing a first outputbuffer and a second output buffer, said first output buffer receiving anoutput from said single stage buffer and said second output bufferreceiving an output from said constricted inverter.
 11. The methodaccording to claim 8, wherein said single stage buffer includes an NMOSdevice coupled to VCC and a PMOS device coupled to VSS.
 12. The methodaccording to claim 8, wherein said constricted inverter includes a firstPMOS device coupled to VCC, a first NMOS device coupled to VSS a secondNMOS device coupled to said first PMOS device and a second PMOS devicecoupled to said first NMOS device.
 13. A clock splitter apparatuscomprising: a single stage buffer; a constricted inverter; a first inputto provide an input clock signal to both said single stage buffer andsaid constricted inverter; a clock output coupled to the output of saidsingle stage buffer to provide a clock output signal; and an invertedclock output signal coupled to an output of said constricted inverter toprovide an inverted output signal.
 14. The clock splitter apparatusaccording to claim 13, wherein said clock output signal and saidinverted clock output signal have low skew with respect to each other.15. The clock splitter apparatus according to claim 13, wherein saidsingle stage buffer and constricted inverter include PMOS and NMOStransistors which are sized in regard to each other to give equal riseand fall edge rates and which cause similar delay times in said singlestage buffer and said constricted inverter so as to produce low skew.16. The clock splitter according to claim 13, wherein said single stagebuffer includes an NMOS device coupled to VCC and a PMOS device coupledto VSS.
 17. The clock splitter according to claim 13, wherein theconstricted inverter includes a first PMOS device coupled to VCC, afirst NMOS device coupled to VSS, a second NMOS device coupled to saidfirst PMOS device and a second PMOS device coupled to said first NMOSdevice.
 18. The clock splitter according to claim 13, further comprisinga first output buffer and a second output buffer, said first outputbuffer receiving the output of said single stage buffer and having anoutput coupled to said clock output; said second output buffer having aninput coupled to the output of said constricted inverter and an outputcoupled to said inverted clock output.
 19. A clock splitter according toclaim 13, further comprising an input buffer to receive said input clocksignal and to produce an output coupled to the input of both said singlestage buffer and constricted inverter.
 20. A method of producing aclock/inverted clock signal pair, comprising: providing a first part toproduce a clock output signal and a second part to produce an invertedclock output signal; delaying said clock output signal and said invertedclock output signal equally in said first and second parts by matchingsaid transistors in said first part and said second part; delaying saidclock output signal and said inverted clock output signal equally insignal paths leading to said first part and said second part by matchingsignal path lengths and areas; and said clock output signal and saidinverted clock output signal having low skew in relation to each other.21. The method according to claim 20, further comprising: providing aninput buffer for receiving an input clock signal and providing a commonclock signal to said first part and said second part.